1. Field of the Invention
The present invention relates to a technology for ensuring synchronization between a processor and a coprocessor, and particularly relates to a synchronous signal producing circuit, which controls a data ready signal indicating an end of access to a shared memory, and thereby controls synchronization between the processor and the coprocessor, as well as a processor system and a synchronizing method using such a circuit.
2. Description of the Background Art
In recent years, fast processors have been employed in information processing equipment such as a personal computer as well as home electrical equipment, and it has been increasingly demanded to improve processing speeds. As a measure for improving the processing speeds, a coprocessor may be employed in addition to a processor so that the coprocessor may perform complicated arithmetic operations which cannot be efficiently done by the processor. A shared memory which can be accessed from both the processor and the coprocessor may be used for data transmission between the processor and coprocessor. This is effective at reducing data transferring operations.
In a system using the processor and coprocessor, the processor issues a coprocessor instruction to the coprocessor. After the coprocessor executed the coprocessor instruction, the result of execution is stored in the shared memory. While the coprocessor is executing the coprocessor instruction, the processor performs another operation in parallel. For utilizing the result of execution of the coprocessor instruction by the processor, the processor must access a region of the shared memory storing the result of execution of the coprocessor instruction after completion of the coprocessor instruction. This is referred to as “synchronization”, “to synchronize” or the like in this specification.
If the processor uses data in a region of the shared memory, where the execution result of the coprocessor instruction is to be stored, before completion of the coprocessor instruction, this results in an erroneous operation. For avoiding this erroneous operation, such a manner is employed that the processor polls status flags in the coprocessor indicating the status of the coprocessor instruction processing, or receives an interrupt request sent from the coprocessor, and thereby the processor confirms the completion of the coprocessor instruction so that the processor and coprocessor are synchronized.
However, the foregoing manner in which the processor polls the status flags in the coprocessor requires a wasteful operation cycle for polling by the processor, and therefore suffers from a problem of reduction in operation speed. The manner in which the processor receives the interrupt request from the coprocessor requires overhead such as saving/restoring for a register is required for processing the interrupt processing. This also reduces the operation speed of the processor.